This application is a Divisional of copending application Ser. No. 11/073,676 filed on Mar. 8, 2005 now U.S. Pat. No. 7,190,066 the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. § 120.
The invention relates to a package structure, and more specifically to a package structure with improved reliability.
As semiconductor device circuit density increases and device feature size decreases, increased numbers of patterned metal levels are required with decreased spacing between metal lines at each level to effectively interconnect discrete devices on semiconductor chips. Layers of insulating materials or films, typically referred as inter-layer dielectric (ILD) layers, separate different levels of metal interconnections. A common insulating material used for ILD layers is silicon oxide having a dielectric constant (k) of about 4.0 to 4.5 relative to vacuum having a k value of 1.0. Unfortunately, as the spacing between the metal lines decreases, the intra-level and inter-level capacitances therebetween increases, as capacitance is inversely proportional to the spacing therebetween. It is therefore desirable to minimize the dielectric constant k of the insulating material between the metal lines to reduce the RC time constant, and thus, the performance of the circuit, e.g., the frequency response or the like, is improved since the signal propagation time in the circuit is adversely affected by the RC delay time.
When an insulating material having a dielectric constant k less than 3, often referred to as a low k material, is utilized as ILD layers between the metal lines, the adhesion between the low k material and metal line, however, is weaker than that between silicon oxide and metal line. Further, the linear thermal expansion coefficient of a conventional encapsulant for a package is typically larger than 10 ppm/° C., and that of silicon, one of the popular semiconductor materials, is approximately 3 ppm/° C. Thus, high thermal expansion coefficient mismatch therebetween results in exertion of thermal stress between a chip and encapsulant in the package. When a low k material is used for ILD layers in the chip, the ILD layers suffer more potential of delamination resulting from the exertion of thermal stress during assembly.